DRAM arrays typically include adjacent capacitors between which isolated electrical contact must be made to a transistor for a DRAM bit line. Such contact is typically provided by use of a photoresist masking step which must be critically aligned relative to the adjacent capacitors to assure that the bit contact and capacitors do not short. To allow for inevitable mask misalignment, the capacitors are typically spaced farther apart than would otherwise by required if risk of photoresist mask misalignment were not an issue. However, the added space typically provided for mask misalignment undesirably defeats the goal of maximizing circuit density.
Accordingly, needs remain for increasing the target area for the contact etch between adjacent capacitors without consuming precious substrate area. Although the invention arose from problems associated with forming a bit line contact between adjacent capacitors, the artisan will appreciate applicability of the invention to other aspects of semiconductor wafer processing where contacts are formed intermediate to adjacent electrical components.